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hexfet ? power mosfet v dss = 55v r ds(on) = 8.0m i d = 42a this hexfet ? power mosfet utilizes the latest processing techniques to achieve extremely lowon-resistance per silicon area. additional features of this design are a 175c junction operating temperature, fast switching speed and improved repetitive avalanche rating. these features combine to make this design an extremely efficient and reliable device for use in a wide variety of applications. s d g description logic level advanced process technology ultra low on-resistance 175c operating temperature fast switching repetitive avalanche allowed up to tjmax lead-free features d-pak irlr3705zpbf i-pak irlu3705zpbf irlr3705zpbfirlu3705zpbf absolute maximum ratin g s parameter units i d @ t c = 25c continuous drain current, v gs @ 10v (silicon limited) i d @ t c = 100c continuous drain current, v gs @ 10v a i d @ t c = 25c continuous drain current, v gs @ 10v (package limited) i dm pulsed drain current p d @t c = 25c power dissipation w linear derating factor w/c v gs gate-to-source voltage v e as (thermally limited) single pulse avalanche energy mj e as (tested ) single pulse avalanche energy tested value i ar avalanche current a e ar repetitive avalanche energy mj t j operating junction and t stg storage temperature range c soldering temperature, for 10 seconds mounting torque, 6-32 or m3 screw thermal resistance parameter typ. max. units r jc junction-to-case CCC 1.14 r ja junction-to-ambient (pcb mount) CCC 40 c/w r ja junction-to-ambient CCC 110 190 110 see fig.12a, 12b, 15, 16 130 0.88 16 max. 8963 360 42 -55 to + 175 300 (1.6mm from case ) 10 lbf in (1.1n m) pd - 95956a downloaded from: http:///

2 www.irf.com s d g electr i cal c haracter i st i cs @ t j = 25 c ( unless otherw i se spec ifi ed ) parameter min. typ. max. units v (br)dss drain-to-source breakdown voltage 55 CCC CCC v ? v (br)dss / ? t j breakdown voltage temp. coefficient CCC 0.053 CCC v/c r ds(on) static drain-to-source on-resistance CCC 6.5 8.0 m CCC CCC 11 CCC CCC 12 v gs(th) gate threshold voltage 1.0 CCC 3.0 v gfs forward transconductance 89 CCC CCC s i dss drain-to-source leakage current CCC CCC 20 a CCC CCC 250 i gss gate-to-source forward leakage CCC CCC 200 na gate-to-source reverse leakage CCC CCC -200 q g total gate charge CCC 44 66 q gs gate-to-source charge CCC 13 CCC nc q gd gate-to-drain ("miller") charge CCC 22 CCC t d(on) turn-on delay time CCC 17 CCC t r rise time CCC 150 CCC t d(off) turn-off delay time CCC 33 CCC ns t f fall time CCC70CCC l d internal drain inductance CCC 4.5 CCC between lead, nh 6mm (0.25in.) l s internal source inductance CCC 7.5 CCC from package and center of die contact c iss input capacitance CCC 2900 CCC c oss output capacitance CCC 420 CCC c rss reverse transfer capacitance CCC 230 CCC pf c oss output capacitance CCC 1550 CCC c oss output capacitance CCC 320 CCC c oss eff. effective output capacitance CCC 500 CCC source-drain ratin g s and characteristics parameter min. typ. max. units i s continuous source current CCC CCC 42 (body diode) a i sm pulsed source current CCC CCC 360 (body diode) v sd diode forward voltage CCC CCC 1.3 v t rr reverse recovery time CCC 21 42 ns q rr reverse recovery charge CCC 14 28 nc t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by ls+ld) v gs = 16v v gs = -16v v ds = v gs , i d = 250a v ds = 55v, v gs = 0v v ds = 55v, v gs = 0v, t j = 125c v ds = 44v v ds = 25v, i d = 42a i d = 42a conditions v gs = 5.0v v gs = 0v v ds = 25v ? = 1.0mhz v gs = 0v, v ds = 1.0v, ? = 1.0mhz v gs = 0v, v ds = 44v, ? = 1.0mhz v gs = 0v, v ds = 0v to 44v mosfet symbol showing the integral reverse p-n junction diode. t j = 25c, i s = 42a, v gs = 0v t j = 25c, i f = 42a, v dd = 28v di/dt = 100a/s conditions v gs = 0v, i d = 250a reference to 25c, i d = 1ma v gs = 4.5v, i d = 21a v gs = 10v, i d = 42a v gs = 5.0v, i d = 34a v gs = 5.0v v dd = 28v i d = 42a r g = 4.2 downloaded from: http:///

www.irf.com 3 fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics fig 4. typical forward transconductance vs. drain current 0.1 1 10 100 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 60s pulse width tj = 25c 2.8v vgs top 12v 10v 8.0v 5.0v 4.5v 3.5v 3.0v bottom 2.8v 0.1 1 10 100 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 60s pulse width tj = 175c 2.8v vgs top 12v 10v 8.0v 5.0v 4.5v 3.5v 3.0v bottom 2.8v 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 v gs , gate-to-source voltage (v) 1.0 10.0 100.0 1000.0 i d , d r a i n - t o - s o u r c e c u r r e n t ( ) v ds = 15v 60s pulse width t j = 25c t j = 175c 0 1020304050607080 i d, drain-to-source current (a) 0 20 40 60 80 100 g f s , f o r w a r d t r a n s c o n d u c t a n c e ( s ) t j = 25c t j = 175c v ds = 8.0v 380s pulse width downloaded from: http:///

4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 1 10 100 v ds , drain-to-source voltage (v) 0 1000 2000 3000 4000 5000 c , c a p a c i t a n c e ( p f ) coss crss ciss v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 0 2 04 06 08 01 0 0 q g total gate charge (nc) 0 2 4 6 8 10 12 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 44v vds= 28v vds= 11v i d = 42a 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 v sd , source-to-drain voltage (v) 0.1 1.0 10.0 100.0 1000.0 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v 1 10 100 v ds , drain-tosource voltage (v) 0.1 1 10 100 1000 10000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) tc = 25c tj = 175c single pulse 1msec 10msec operation in this area limited by r ds (on) 100sec dc downloaded from: http:///

www.irf.com 5 fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature fig 10. normalized on-resistance vs. temperature 25 50 75 100 125 150 175 t c , case temperature (c) 0 20 40 60 80 100 i d , d r a i n c u r r e n t ( a ) limited by package 1e-006 1e-005 0.0001 0.001 0.01 0.1 t 1 , rectangular pulse duration (sec) 0.001 0.01 0.1 1 10 t h e r m a l r e s p o n s e ( z t h j c ) 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc ri (c/w) i (sec) 0.6984 0.0004650.4415 0.004358 j j 1 1 2 2 r 1 r 1 r 2 r 2 c ci i / ri ci= i / ri -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.5 1.0 1.5 2.0 2.5 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 42a v gs = 10v downloaded from: http:///

6 www.irf.com q g q gs q gd v g charge fig 13b. gate charge test circuit fig 13a. basic gate charge waveform fig 12c. maximum avalanche energy vs. drain current fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as fig 14. threshold voltage vs. temperature r g i as 0.01 t p d.u.t l v ds + - v dd driver a 15v 20v v gs 1k vcc dut 0 l 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 100 200 300 400 500 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top 5.3a 7.0a bottom 42a -75 -50 -25 0 25 50 75 100 125 150 175 t j , temperature ( c ) 0.0 0.5 1.0 1.5 2.0 2.5 v g s ( t h ) g a t e t h r e s h o l d v o l t a g e ( v ) i d = 250a i d = 150a i d = 50a downloaded from: http:///

www.irf.com 7 fig 15. typical avalanche current vs.pulsewidth fig 16. maximum avalanche energy vs. temperature notes on repetitive avalanche curves , figures 15, 16:(for further info, see an-1005 at www.irf.com) 1. avalanche failures assumption: purely a thermal phenomenon and failure occurs at a temperature far in excess of t jmax . this is validated for every part type.2. safe operation in avalanche is allowed as long ast jmax is not exceeded. 3. equation below based on circuit and waveforms shown in figures 12a, 12b. 4. p d (ave) = average power dissipation per single avalanche pulse.5. bv = rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. i av = allowable avalanche current. 7. ? t = allowable rise in junction temperature, not to exceed t jmax (assumed as 25c in figure 15, 16). t av = average time in avalanche. d = duty cycle in avalanche = t av f z thjc (d, t av ) = transient thermal resistance, see figure 11) p d (ave) = 1/2 ( 1.3bvi av ) = t/ z thjc i av = 2 t/ [1.3bvz th ] e as (ar) = p d (ave) t av 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 tav (sec) 0.1 1 10 100 1000 a v a l a n c h e c u r r e n t ( a ) 0.05 duty cycle = single pulse 0.10 allowed avalanche current vs avalanche pulsewidth, tav assuming ? tj = 25c due to avalanche losses. note: in no case should tj be allowed to exceed tjmax 0.01 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 20 40 60 80 100 120 e a r , a v a l a n c h e e n e r g y ( m j ) top single pulse bottom 1% duty cycle i d = 42a downloaded from: http:///

8 www.irf.com fig 17.
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? ? p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-appliedvoltage reverserecovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period #
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# $$ ? !"!!%" v ds 90%10% v gs t d(on) t r t d(off) t f &' 1 (
# 0.1 % + - fig 18a. switching time test circuit fig 18b. switching time waveforms downloaded from: http:///

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international as s e mbled on ww 16, 2001 in the assembly line "a" or note: "p" in as s embly line pos ition example: lot code 1234 this is an irfr120 wi t h as s e mb l y i ndi cates "l ead-f r ee" product (optional) p = des ignat e s le ad-free a = as s e mb l y s i t e code part number we e k 1 6 dat e code ye ar 1 = 2001 rectifier international logo lot code as s e mb l y 34 12 irf r120 116a line a 34 rectifier logo irf r120 12 as s e mb l y lot code ye ar 1 = 2001 dat e code part number we e k 1 6 "p" in assembly line position indicates "l ead- f r ee" qual i fi cati on to the cons umer -l evel p = des ignat e s le ad-free product qualified to the consume r le vel (opt ional) notes: 1. for an automotive qualified version of this part please see http://www.irf.com/product-info/auto/ 2. for the most current drawing please refer to ir website at http://www.irf.com/package/ downloaded from: http:///

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78 line a logo international rectifier or product (opt ional) p = des ignat e s lead-f ree a = assembly site code irfu120 part number we e k 1 9 dat e code year 1 = 2001 rectifier international logo as s e mb l y lot code irfu120 56 dat e code part numbe r lot code as s e mb l y 56 78 year 1 = 2001 we e k 1 9 119a i ndi cates l ead- f r ee" as s embled on ww 19, 2001 in the assembly line "a" note: "p" in assembly line position example: wi t h as s e mb l y this is an irfu120 lot code 5678 notes: 1. for an automotive qualified version of this part please see http://www.irf.com/product-info/auto/ 2. for the most current drawing please refer to ir website at http://www.irf.com/package/ downloaded from: http:///

www.irf.com 11 data and specifications subject to change without notice. this product has been designed for the industrial market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 10/2010 repetitive rating; pulse width limited by max. junction temperature. (see fig. 11). limited by t jmax , starting t j = 25c, l = 0.12mh r g = 25 , i as = 42a, v gs =10v. part not recommended for use above this value. pulse width 1.0ms; duty cycle 2%.
c oss eff. is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss . limited by t jmax , see fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. this value determined from sample failure population. 100% tested to this value in production. when mounted on 1" square pcb (fr-4 or g-10 material) . for recommended footprint and soldering techniques refer to application note #an-994
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tr 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) 12.1 ( .476 ) 11.9 ( .469 ) feed direction feed direction 16.3 ( .641 ) 15.7 ( .619 ) trr trl notes : 1. controlling dimension : millimeter. 2. all dimensions are shown in millimeters ( inches ). 3. outline conforms to eia-481 & eia-541. notes : 1. outline conforms to eia-481. 16 mm 13 inch downloaded from: http:///

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